Rebuilding a 180 nm SRAM without touching a transistor

This started with a teardown. The GF180MCU open PDK ships a family of small SRAM macros, and I wanted to know why a 4 kilobit one was the size it was. So I opened the GDS and measured. The answer surprised me: only 26.4% of the macro is bitcells. The other three quarters is decoders, sense amplifiers, timing circuits, and rings — and you pay for all of it again every 4 kb. Build a 32-bit memory and you place four macros side by side: four decoders, four timing generators, four of everything.

The obvious first instinct is to shrink the bitcell. I measured it instead. The cell is 13.5 µm² at its placement pitch, and when you check the spacings across the cell-to-cell seams, the numbers are 0.361 µm against a 0.36 rule and 0.241 against a 0.24 rule — one database grid unit of slack, which is to say none. The people who drew this cell knew exactly what they were doing. The foundry’s own datasheet later confirmed every measurement, and taught me something in the process: the pass gate is 0.6/0.77 — a long-channel pass transistor. They bought cell stability with gate length, not pull-down width. Measuring beats assuming, and when you can check your assumptions against the source, do it twice. So the conclusion wrote itself: the transistors are a solved problem. Leave every one of them alone. The wrapper is the problem.

Where the performance went

Before touching layout I wanted to know where the time went, so I fit a physical model to the foundry’s own characterization data. The result: bitline and wordline physics — the actual array — account for 0.89% of the 4.86 ns access time. The cycle is 43.5 fanout-of-4 delays, which for an SRAM is enormous. It isn’t badly designed; it’s conservatively designed, with fixed worst-case margins everywhere. It will work on any wafer that comes back. It is also paying rent it doesn’t need to pay.

The vertical move

gf180mcuD has five metal layers, the top one 1.19 µm of thick aluminium rated for serious current. The shipped macro uses three of them; the datasheet even advertises “minimum 3 layers of metals required.” Metals 4 and 5 over the array are empty sky. That emptiness is the resource. We moved the power grid up: 1.1 µm Metal4 strap pairs that tuck into strap-column slots the array already has (zero silicon cost), and 4 µm Metal5 rails above everything, worth 0.61% IR drop at 256 kb.

Moving wires up doesn’t shrink a cell — and can’t: the cells were already at the rule floor. What it buys is architecture. Freed from the three-metal budget, one decoder and one sense stripe can serve 512 columns of a ×32-wide word, with the array split into four 128-row banks so the bitlines stay short. The periphery that used to be 74% of every little macro gets amortized across 64× more bits. And the decoder itself? Re-tiled from the shipped macro’s own decoder cells, polygon for polygon, to within 0.04 µm of the width we predicted. Reuse is a strategy, not a shortcut.

Speed came along for free

The same work replaced the fixed self-timing margins with a replica bitline — a dummy column built from the same proven cells, so its delay tracks the real array across process and temperature instead of budgeting for the worst case. Result: 29.9 FO4 at typical (we wanted 25; the levers to get to ~21 are identified), projecting to 115.8 MHz at the slow corner versus the shipped macro’s 84. Crossing 100 MHz matters for a specific reason: it means a dual-port 2 KB scratchpad can be built as two single-port banks running at double the bus clock — full dual-port behavior from plain, silicon-proven 6T cells. The best custom bitcell is the one you don’t have to design.

What verification actually caught — and what fixing it taught us

The full 4.5 mm² macro passes the foundry’s complete DRC deck with zero violations of our own. But DRC checks geometry, not circuits. An explicit via audit found every Metal4/Metal5 via properly enclosed — and zero via3 anywhere. The beautiful power canopy was not connected to the array below it. DRC will happily bless a flashlight with no battery in it.

The fix was a classification problem before it was a via problem: Metal3 carries both the strap-column power rails and the horizontal wordline straps, and a blind via drop would short every wordline to the supply. So we classified first — every Metal3 shape in the array, power or wordline, with polarity traced down to the Metal1 rails it feeds. Then the surprise: all of the array’s strap-column Metal3 turned out to be VSS. The foundry cell routes VDD by another path entirely. The layout had an opinion nobody had written down.

The result: 34,460 via3 cuts in 17,230 classified windows, every one at least 1.34 µm clear of a wordline band. The connectivity extraction — the check DRC fundamentally cannot do — proved VSS was one electrical net from the Metal5 rails down to all 345,284 Metal1 cell rails, with no wordline joined to it. The antenna deck, run for the first time over this geometry: zero violations. VDD took a second pass, because tracing showed the foundry cell delivers it by a different route entirely — a separate Metal2 strap and an N‑well tap rail, with zero via2 on either power strap as shipped. New Metal3 landing patches fixed that, and both rails came back as single nets.

The same trick catches the same bug twice

Feeling good about a connected power grid, I ran the audit again — this time asking not “are there vias” but “where aren’t there vias.” Bucket every cut into 20 µm bands across the macro and look for empty ones. There was a run of empty bands at the west edge, 174 µm wide.

That strip is the row decoder. Metal4, Metal5 and via3 all began at x = 0; the macro begins at −174. The decoder had been placed, DRC‑checked, and celebrated — and it had no connection to the power grid at all. Worse, the connectivity proof I had been quoting was clean precisely because all thirteen of its probes sat inside the array. A proof only covers what you point it at. The array was fed; the thing that drives the wordlines was not.

The fix followed the same measure‑first pattern, and the foundry cells helped again: the decoder cells carry vdd and vss labels on their own Metal3 rails — 1,226 of them. Rather than guess polarity, derive it: Metal4 line polarity from the drawn slot pattern (cross‑checked against the recorded probes), Metal5 rail polarity from which Metal4 lines each rail’s via4 cuts land on (a clean 70/69 alternation fell out), and the decoder’s own polarity from its labels. Then extend the canopy west and stitch it down: 139 Metal5 rails extended, two new Metal4 lines, 266 via4, 854 via3 onto 440 decoder rails.

This time the proof was pointed at the right place. Probes inside the decoder now report its VSS line on the array’s VSS net and its VDD line on the array’s VDD net; all 608 VDD and 618 VSS decoder rails resolve to exactly those two nets and nothing else; the rails stay disjoint. The DRC run over the patched macro was still going when this paragraph was written, which is the honest state of it.

One more, because it is the kind of thing that never shows up in a picture. The first patched build came back with four fresh violations of V3.1 — the rule that says a via edge must be exactly 0.26 µm. The flagged edges were 0.261. One decoder rail happens to sit on a half‑nanometre centre, and computing a cut as “centre ± half a via” rounded outward by a single database unit. Nothing is visibly wrong at any zoom level; the geometry is simply one nanometre too big, 854 times over, and the deck is right to reject it. Cuts are now built in integer database units, so the drawn size is exact regardless of where the measured centre falls — all 182,176 via3 and via4 cuts verify at exactly 0.26 square.

Where it actually goes

A macro is not a chip. The first time we measured the finished 256 kb block against the shuttle slot we had been assuming — 1.94 × 2.53 mm — it did not fit. Not “tight”: the macro is 1963 µm wide and the entire die is 1936. That is the sort of thing you want to learn from a script rather than from a rejected submission, and it is exactly what the foundry’s own precheck tool told us in about ninety seconds once we pointed it at the layout.

The obvious response is to shrink the memory to fit. The better response is to take the next slot up. On a 1×1 slot the core is 3048 × 4238 µm, and the full macro lands at 38% of it — with an L-shaped 8 mm² left over that happily holds both foundry reference SRAMs, the BIST, and the test bus. So instead of taping out a scaled-down demo, we tape out the real thing sitting next to the parts it claims to beat, on the same die, from the same wafer, measured at the same corner. Every comparison stops being an argument about datasheets.

Why this is worth doing in the open

Nothing here required new masks, new devices, or foundry favors. The bitcells are the foundry’s own Apache-2.0 polygons, untouched down to their waiver markers. The upper metals exist on every wafer already. Every number above traces to a rule quoted from the PDK’s DRC deck, a value from its technology files, or a circuit simulation with its device models — and every artifact regenerates from scripts. Since the first draft: both supply rails are connected and proven, the decoder stripe is placed and now stitched to the canopy, and the target moved to a 1×1 slot. The four custom periphery cells are drawn — the replica head at 27.0 × 11.4 µm dropping straight onto the array’s 27 µm column pitch, the timing control block at 82.2 × 30.35, the spare‑column remap landing at 1.71 FO4 against a 1.88 budget — each DRC‑clean on its own before assembly. What remains is assembly with real signal pins, a LEF with real ports, LVS, parasitic extraction, and characterization to replace projected timing with measured timing. Then the die: padring, seal ring, and the foundry precheck run against the assembled chip rather than the bare macro. After that, a 3.93 × 5.12 mm test chip on a multi-project wafer gets the only vote that counts.

None of this needed a new mask, a new device, or a favour. It needed a PDK you can read, tools that will tell you the truth when you ask them precisely, and the discipline to keep asking after the answer already looks good.